Intel plans flash memory replacement

Intel and Numonyx announced a breakthrough in the development of phase change memory today that has the potential to allow developers to stack multiple layers of chips atop each other, thereby greatly increasing the density of the nonvolatile memory medium.

Calling the discovery a "milestone" in phase change memory (PCM) development, the researchers said they have so far only been able to build a single layer, 64Mbit chip with the potential to be stacked with other 64Mbit chips.

Greg Atwood, a senior technology fellow at Numonyx, said the breakthrough in stackable PCM, which is being called PCM-stackable (PCMS), has the potential to create products that can replace DRAM, NOR and NAND flash memory because it will have better bandwidth, greater density and a cost per gigabyte of capacity comparable with today's solid state drive (SSD) products.

"We believe it enables the possibility of combining the functionality and performance of phase change memory with more NAND-like cost structure," Atwood said. "And, it's of particular interest given the challenges the existing non-volatile memory technologies are facing over the next decade as well as the continued expansion of [PCM] usage."

The two companies have been working on development of PCM products since 2000, and a stackable PCM product since 2002. Al Fazio, an Intel fellow and director of memory technology development, said it's not unusual for a new memory type to take as many as 10 years to develop.

Atwood said that because the stacking breakthrough builds on top of PCM, a technology already in production, "it's a leading candidate amongst the various stackable memory concepts, most of which have no basis in a proven technology."

Other non-volatile memories in development include graphite memory, and race track memory.

Atwood added that Intel and Numonyx have no current time line for bringing PCMS products to market.

Phase change memory is made up of a glass-like material called chalcogenide that can be can be switched between a crystalline and random state using very low-voltage electricity.

Current NAND flash memory lithography technology resides at the 32-nanometer level. Future roadmaps scale NAND flash to 20 nanometers, but physical limitations present a barrier to creating anything more dense than that.

PCM, however, currently has the ability to scale to 5 nanometers in size, and the potential of even greater densities, Fazio said.

The structure of a typical non-volatile memory cell includes a storage element combined with a selector element. The function of the storage element is nonvolatile storage of data and the purpose of the selector element is to connect storage elements into a cross-point array of cells. The connection allows for the selection of a single storage element inside of a large array of cells -- a billion or more.

Unlike NAND flash memory, which requires a entire block of memory cells to be rewritten each time new data is stored on a device like a SSD drive, PCM allows for single bits to be changed, greatly increasing the efficiency and performance of a device.

"It has features of a low-latency memory and high bandwidth so we can combine many of the good attributes ... of NAND flash, DRAM and NOR flash," Fazio said.

The breakthrough in stacking PCMS came with the use of a thin film selector substance that is in the same class of materials as chalcogenide and is built above the silicon substrate. The companies are calling the thin film selector an Ovonic Threshold Switch (OTS), which acts like a resistor between the stacked layers of PCM chips.

"This switch demonstrates a diode-like behavior. It has a low current in the off state and a high current in the on state," Atwood said. "Combining the OTS with the thin film storage material, a similar material used in phase-change memories today, enables a cell that can be stacked multiple layers high." Additionally, since the silicon substrate that isn't being used as a selector, as it is in today's PCM products, can now be used for building the support circuitry used that's required to decode, read and write to the cells.

"So the combination of these two advantages results in a much smaller die size that's a lower potential cost structure for the memory," Atwood said.