IBM makes 3D chips for efficiency

IBM is building space-saving three dimensional chips that stack a processor on top of its memory and power components, and making holes to connect them.

Some chipmakers already stack processors, but connect them with long wires wrapped around the edges of the chips. Others set the chip pairs side by side on a circuitboard. By etching holes straight through the processors, IBM can use wires one-thousandth as long, and use 40 percent less electrical power, said Lisa Su, vice president for IBM's semiconductor research and development centre.

IBM etches the holes with a chemical process in a standard CMOS (complementary metal oxide semiconductor chip. It will be able to deliver samples of the new chips to customers in the second half of 2007 and reach full production in 2008, said Su. The first users will be producers of wireless LAN and cellular communications products.

Next, IBM will apply this "through-silicon-vias" method to its microprocessors, stacking its Power series server chips or Blue Gene supercomputer chips on top of memory storage in order to keep the processors fed with data far faster than current technology allows. Delivering data through stacked holes will let engineers route the memory through 100 times more channels than are now available.

"Today, most chips have two or four cores, and people are saying 'Let's go to eight, 16 or 32.' But in truth what's limiting chip design is how close you can get the memory to the processing core," Su said.

In recent months, IBM has announced several new chip designs for standard, two-dimensional chips, such as "high-k, metal gate" transistors and onboard embedded dynamic RAM (DRAM). The new method will complement those approaches by adding an extra dimension, she said. In the future, IBM could use the technique in more novel designs, stacking two microprocessors on top of each other or building a pile more than two chips high, she said.

The stacked-chip design has so many benefits that a handful of startup companies are already trying to apply the same technique to niche applications, stacking sensor arrays and imaging processing logic to improve military optics, said Dave Lammers, director of www.WeSRCH.com for VLSI Research Inc.

But no vendor has shipped a commercial version yet, and IBM's announcement could push major PC chipmakers to adopt it for their own chips. Intel and AMD will probably be using versions of the technology as soon as 2010, he said.

"This is a huge breakthrough. Since the mid-60s we've just used the X and Y dimensions of integrated circuits. Now we can use this new approach to get around some huge problems. The bandwidth between logic and memory will go up, and it could help with the problem of power and heat dissipation," said Lammers.